The Taiwan Semiconductor Manufacturing Company (TSMC) has reported impressive yields for its next-generation chip manufacturing technology. Dubbed as the N3e, this technology is an upgrade over TSMC’s first iteration of the N3 node, which expects to shrink down some transistor dimensions to as low as 3-nanometer. Today’s report comes courtesy of Morgan Stanley, who has released a new research report titled “Production yield of N3e is higher than expected; reiterate OW” and shared on Twitter.
TSMC Moves Forward N3E Production By A Full Quarter Believes Investment Bank Morgan Stanley
A snippet of the report has been shared on the social media platform Twitter by the user going by the name Retired Engineer. This snipped cites Morgan Stanley’s checks with equipment vendors to suggest that TSMC might “freeze” its design parameters for the N3E node as soon as by the end of this month. This is due to better than expected yield for the process and it indicates that volume production for the process, which is one of the final stages before a chip node enters mass production, might start by the second quarter of next year. The snippet, shared by the Twitter user, states that: Morgan Stanley’s news comes after sources in the Taiwanese press had speculated that TSMC is facing troubles with its 3nm yield. In the semiconductor industry, the yield of a process is defined as the number of chips that pass quality control checks on a single wafer, and the higher the percentage, the more mature a process is. Fabs such as TSMC often take their time to perfect this metric as it deepens their customer relationships and improves the quality of their products. It also mentions the existence of an N3b node, which had previously been speculated to have been introduced as a stop-gap measure by TSMC due to poor yields. While the earlier reports had speculated that TSMC’s customers had chosen to stick with the relatively mature 5nm node due to the alleged yield defects, whether this still remains to be the case is uncertain. TSMC’s official figures for the original N3 node shared last year outlined that the process has 70% greater density over the 5nm process. Morgan Stanley’s figure of a 60% increase over 5nm, and an 8% reduction over the first generation N3 follows in line with the estimates shared by the chip manufacturer. The N3E node will “feature improved manufacturing process window with better performance, power and yield,” outlined TSMC’s chief executive officer Dr. C.C. Wei during the company’s third-quarter 2021 investor call last year. The fab is currently competing with U.S. chip giant Intel Corporation in developing the latest chip manufacturing technologies, and at this front, both are in a race to acquire new machines and reduce transistor sizes while being able to streamline production and meet market demand. The third chip maker in the world capable of manufacturing on the latest nodes, Samsung Foundry, is allegedly investigating fraud within its ranks related to manufacturing process yield.
